In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations.
Internal circuitry in the memory device generates an internal clock signal that is synchronized with the external clock signal and is used to synchronize internal and external operations. To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. FIG. 1 is a functional block diagram illustrating a conventional delay-locked loop 100 including a variable delay line 102 that receives a clock buffer signal CLKBUF and generates a delayed clock signal CLKDEL in response to the clock buffer signal. The variable delay line 102 controls a variable delay VD of the CLKDEL signal relative to the CLKBUF signal in response to a delay adjustment signal DADJ. A feedback delay line 104 generates a feedback clock signal CLKFB in response to the CLKDEL signal, the feedback clock signal having a model delay D1+D2 relative to the CLKDEL signal. The D1 component of the model delay D1+D2 corresponds to a delay introduced by an input buffer 106 that generates the CLKBUF signal in response to an external clock signal CLK, while the D2 component of the model delay corresponds to a delay introduced by an output buffer 108 that generates a synchronized clock signal CLKSYNC in response to the CLKDEL signal. Although the input buffer 106 and output buffer 108 are illustrated as single components, each represents all components and the associated delay between the input and output of the delay-locked loop 100. The input buffer 106 thus represents the delay D1 of all components between an input that receives the CLK signal and the input to the variable delay line 102, and the output buffer 108 represents the delay D2 of all components between the output of the variable delay line and an output at which the CLKSYNC signal is developed.
The delay-locked loop 100 further includes a phase detector 110 that receives the CLKFB and CLKBUF signals and generates a delay control signal SL/SR having a value indicating the phase difference between the CLKBUF and CLKFB signals. A delay controller 112 generates the DADJ signal in response to the SL/SR signal from the phase detector 110, and applies the DADJ signal to the variable delay line 102 to adjust the variable delay VD. The phase detector 110 and delay controller 112 operate in combination to adjust the variable delay VD of the variable delay line 102 as a function of the detected phase between the CLKBUF and CLKFB signals.
In operation, the phase detector 110 detects the phase difference between the CLKBUF and CLKFB signals, and the phase detector and delay controller 112 operate in combination to adjust the variable delay VD of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. More specifically, as the variable delay VD of the CLKDEL signal is adjusted the phase of the CLKFB signal from the feedback delay line 104 is adjusted accordingly until the CLKFB signal has approximately the same phase as the CLKBUF signal. When the delay-locked loop 100 has adjusted the variable delay VD to a value causing the phase shift between the CLKBUF and CLKFB signals to equal approximately zero, the delay-locked loop is said to be “locked.” When the delay-locked loop 100 is locked, the CLK and CLKSYNC signals are synchronized. This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop 100 is locked), the variable delay VD has a value of NTCK−(D1+D2) as indicated in FIG. 1, where N is an integer and TCK is the period of the CLK signal. When VD equals NTCK−(D1+D2), the total delay of the CLK signal through the input buffer 106, variable delay line 102, and output buffer 108 is D1+NTCK−(D1+D2)+D2, which equals NTCK. Thus, the CLKSYNC signal is delayed by NTCK relative to the CLK signal and the two signals are synchronized since the delay is an integer multiple of the period of the CLK signal. Referring back to the discussion of synchronous memory devices above, the CLK signal corresponds to the external clock signal and the CLKSYNC signal corresponds to the internal clock signal.
FIG. 2 illustrates the phase detector 110. The phase detector 110 includes a phase detection (PD) window 156 that provides an initial delay of tPDW to the CLKFB signal 134 to generate a delayed feedback clock signal CLKFB2D 157 at an output. Another delay element 158 provides a tPDW/2 delay half of the delay provided by the coarse PD window 156) to CLKBUF 130 to generate a delayed reference clock signal CLKBUFD 159 at an output. The CLKBUFD signal 159 clocks D flip-flops 160, 162 to sample the CLKFB signal 134 and the CLKFB2D signal 157. The output signals PH1 164 and PH2 165 of the D flip-flops 162 and 160, respectively, represent the value of their respective D inputs (CLKFB 134 or CLKFB2D 157) sampled at the rising edge of CLKBUFD 159. The values of the PH1 and PH2 signals represent the phase of the CLKFB signal 134 relative to the CLKREF signal 130. The phase relationship between the PH1 signal 164 and the PH2 signal 165 determines whether to shift the CLKBUF signal 130 earlier or later in time relative to the CLKFB signal 134.
A majority filter 166 receives the PH1 and PH2 signals 164, 165 and a counting clock signal CCLK (not shown) as inputs. The CCLK signal may be the same as the system clock or the CLKBUF signal 130. The majority filter 166 generates an appropriate SL/SR signal as the output 153 of the phase detector 150. As known in the art, the majority filter 166 may include a binary up/down counter clocked by the CCLK signal, which is incremented or decremented in accordance with the levels of the PH1, PH2 signals 164, 165. Alternatively, the majority filter 166 includes a bi-directional shift register that is clocked by the CCLK signal, the direction of the shifting in accordance with the PH1, PH2 signals 164, 165. The majority filter 166 is typically used as a lowpass event filter by counting a certain number of input clock pulses of the CCLK signal (i.e., events) in the same direction (incrementing or decrementing the counter in accordance with the PH1, PH2 signals) before generating an SL or SR signal as an output. For example, the majority filter 166 may always count two clock cycles (events) of the CCLK signal incrementing or decrementing the counter before generating an SL or SR signal as an output. In this manner, clock jitter due to minor fluctuations in operating conditions can be avoided since not every change in the levels of the PH1, PH2 signals will immediately cause an adjustment to be made to the variable delay line 102.
A potential problem with using a binary up/down counter or a bi-directional shift register is that these circuits are reset upon reaching the count value that causes the output of an output signal. For example, in the case a bi-directional shift register is used, an initial condition is usually set from which the bit is shifted in response to the PH1 and PH2 signals. Assuming that two shifts (i.e., two cycles of the CCLK signal) in one direction are required before generating an output signal, when the second shift in the same direction occurs and the output signal is generated, the bi-directional shift register needs to be reset to the initial condition before it can resume shifting in accordance with the PH1, PH2 signals. Resetting the initial condition for the shift register requires a finite time and consumes power. Where the reset time is less than the period of the CCLK signal, all clock cycles can be registered by the shift register. However, where the period of the CCLK signal is less than the reset time, any clock cycles of the CCLK signal that occur during the reset time will not be registered by the shift register, thereby introducing inaccuracies to the delay adjustment.
The same issue arises for a binary up/down counter where the count begins at an initial value, which is then incremented or decremented in response to the CCLK signal and in accordance with the PH1, PH2 signals. Upon reaching the count value to generate an output signal, the counter is reset to the initial count value. As with the use of a bi-directional shift register, the reset operation requires a finite time to complete. During this time, any cycles of the CCLK signal will not result in incrementing or decrementing the count, which results in missing counts. As higher frequency clock signals are utilized for the CCLK signal, more missing counts or lost shifts will occur.
Therefore, there is a need for a event filter that accurately track the occurrence of high frequency events.